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Keywords
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Dynamic comparator, ADC, Low power, Latch Preamplifier, IoT applications
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Abstract
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In this paper, a low power and low delay comparator circuit for the IoT applications has been designed and analyzed. In the proposed comparator, two different voltage levels have been used for the preamplifier and latch sections to control delay and power consumption. To increase the difference between the outputs in the preamplifier structure, two inverter in the inputs has been used. This technique reduces the delay of the comparator outputs. In order to reduce power consumption, the latch section is designed by using SCPG transistors. The operation frequency of this circuit is 50 MHz. In this frequency, the delay and power consumption are 340 ps and 3.55 μW, respectively. The input offset voltage is about 0.6 mV. The circuit has been designed and simulated in 65 nm CMOS technology and the chip area is 230μm2.
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